As feature sizes continue to shrink, improvements, whether in materials, unit processes, or process sequences, are continually being sought for the deposition processes. However, semiconductor companies conduct R&D on full wafer processing through the use of split lots, as the deposition systems are designed to support this processing scheme. This approach has resulted in ever escalating R&D costs and the inability to conduct extensive experimentation in a timely and cost effective manner.
As an example, integrated circuit (IC) manufacturing typically includes a series of processing steps such as cleaning, surface preparation, deposition, lithography, patterning, etching, planarization, implantation, thermal annealing, and other related unit processing steps. The precise sequencing and integration of the unit processing steps enables the formation of functional devices meeting desired performance metrics such as speed, power consumption, and reliability.
The drive towards ever increasing performance of devices or systems of devices such as in systems on a chip (SOCs) has led to a dramatic increase in the complexity of process sequence integration and device integration, or the means by which the collection of unit processing steps are performed individually and collectively in a particular sequence to yield devices with desired properties and performance. This increase in complexity of device integration has driven the need for, and the subsequent utilization of increasingly complex processing equipment with precisely sequenced process modules to collectively perform an effective unit processing step.
The ability to process uniformly across an entire monolithic substrate and/or across a series of monolithic substrates is advantageous for manufacturing cost effectiveness, repeatability and control when a desired process sequence flow for IC manufacturing has been qualified to provide devices meeting desired yield and performance specifications. However, processing the entire substrate can be disadvantageous when optimizing, qualifying, or investigating new materials, new processes, and/or new process sequence integration schemes, since the entire substrate is nominally made the same using the same material(s), process(es), and process sequence integration scheme. Conventional full wafer uniform processing results in fewer data per substrate, longer times to accumulate a wide variety of data and higher costs associated with obtaining such data. As an example, spin coating methods are severely limited in that spin coating methods typically coat an entire substrate surface with a deposition material. In another example, standard mist deposition techniques also lack the ability to provide for combinatorial processing as standard mist deposition techniques typically coat an entire substrate surface with a deposition material. As a result, the manufacture and analysis of a substrate region or structure treated with traditional spin coating or mist deposition techniques require relatively long processing times and increased processing steps. Additionally, the inability to simultaneously deposit multiple thin film regions and multiple materials on a single substrate surface inhibits the ability for comparative analysis between the various regions of a given substrate and/or substrates.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not necessarily restrictive of the invention as claimed. The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the invention and together with the general description, serve to explain the principles of the invention.